1. Field of the Invention
This invention relates to a ball grid array (BGA) semiconductor package, and more particularly to a BGA semiconductor package with enhanced electrical performance and package efficiency.
2. Description of the Related Art
As the demand for the lighter and more complicated semiconductor devices becomes increasing day by day, semiconductor chips become higher in speed and the complication of semiconductor devices thereby brings more electrical connections. The ball grid array (BGA) with high package efficiency has, therefore, been developed by the semiconductor chip packaging industry to meet these needs.
FIGS. 1 and 2 depicts a conventional BGA semiconductor chip package 100 with a chip 101 mounted on a substrate 102 which has a ground ring 103, two power rings 104 and a plurality of fingers 105. A number of bonding pads 106 are connected to the ground ring 103, two power rings 104 and a plurality of fingers 105 by bonding wires 107a-107d respectively. An area array of solder balls 108 are disposed at the lower surface of the substrate 102 for electrically connecting to the ground ring 103, the power ring 104, the fingers 105, the ground plate 103g and the power plate 104p through the vias 103v, 104v and 105v respectively. Each solder ball 108 is used for electrical connection to external circuit, such as a printed circuit board. Finally, a package body (not shown) encapsulates the chip 101, bonding wires 103 and the substrate 102 to form a BGA semiconductor package structure.
In the conventional BGA semiconductor chip package 100, all the ground ring 103, power rings 104 and the fingers 105 are arranged around the chip 101 with different distances and positions with respect to the chip 101, and thus different lengths of bonding wires are required for electrical connection. Accordingly, at least four different looping profiles 107a-107d of the bonding wires are necessary for connecting the bonding pads 106 to the ground ring 103, the power ring 104 and the fingers 105. So. it is necessary to set the operation parameters of wire bonding machine individually for bonding wire with each looping profile and then to operate the wire bonding. It takes four times of each operation to finish the wire bonding process for bonding wire with four looping profiles 107a-107d. More time is consumed for the bonding wire with more types of looping profiles. Furthermore, the more types of looping profiles of the bonding wires will result in the larger height and length of the outer bonding wire, thereby increasing the difficulties of wire bonding operation. For the package having the bonding wires with long and high looping profile, the bonding wire is easily broken especially for that with longer and higher looping profile, and the phenomenon of wire sweep also easily occurs during the encapsulation of package body. Furthermore, the packaging efficiency is reduced because package body with more volume is required to enclose all the bonding wires.
Besides the deficiency in package efficiency as described above, as long as the electrical performance is concerned, the impedance is significantly increased as the length of the bonding wire increases. This influences the electrical performance of BGA semiconductor package. As the bonding wire between the ground ring 103 and the power ring 104 becomes longer, the corresponding inductance and noise therebetween becomes larger. Larger inductance consumes more power in semiconductor package and induces power surges in bonding wire and the integrated circuit of chip 101 easily. In addition, the dispersed distribution of the power via 104v inside the power ring 104 destroys the wholeness of the ground plane 103g, and thus reduces electrical efficiency of ground plane 103g. 
Accordingly, it becomes an important issue to reduce the length and the number of loop profiles of the bonding wire between the ground ring 103 and the power ring 104. Less looping profiles in bonding wire not only can improve electrical performance but also can enhance the package efficiency. Ideally, frequency response between the ground and power rings should be a low pass filter. It can obtain a better frequency response through reducing the inductance and increasing the capacitance of bonding wire. The improved frequency response leads to the operation of the semiconductor package in higher speed, with enhanced electrical performance and less power consumption.
The primary object of the present invention is to provide a novel structure of BGA semiconductor package with less looping profiles and shorter length of the bonding wire between the ground ring and the power ring such that the packaging efficiency can be enhanced.
The secondary object of the present invention is to provide a BGA semiconductor package with less looping profiles and shorter length in the bonding wire between the ground ring and the power ring such that the electrical performance of BGA semiconductor package can be improved.
Another object of the present invention is to provide a BGA semiconductor package with improved frequency response, wherein the semiconductor package can operate in higher speed and with enhanced electrical performance and less power consumption.
To achieve the above objects, according to the first preferred embodiment of the present invention, the chip is mounted on the central region of the upper surface on the substrate. The substrate includes an upper surface, a lower surface, a ground plate disposed under the upper surface, and at least one power plate disposed between the ground plate and the lower surface. A ground ring surrounds the periphery of the chip and possesses a first set of serrated portions extending toward the outer edge of the substrate. A first power ring surrounds the ground ring and possesses a second set of serrated portions extending among the first set of serrated portions of the ground ring, such that the extending portions of the first and second sets of serrated rings interlace coincidentally with each other and the wire bonding distances from the bonding pads of chip to the extending portions of the first and the second serrated rings are comparable. The first power ring also comprises another third set of serrated portions extending toward the outer edge of the substrate. The second power ring surrounds the first power ring and possesses a fourth set of serrated portions extending toward the third serrated ring, such that both the extending portions the third and fourth serrated rings interlace coincidentally with each other and the wire bonding distances from the bonding pads of chip to the extending portions of the third and the fourth serrated rings are comparable. According to the first embodiment of the present invention, only three looping profiles are employed for the bonding wires connecting the bonding pads to the ground ring, the two power rings and the fingers.
According to the second preferred embodiment of the present invention, the chip is mounted on the central region of the substrate, and the first ground ring possesses the first set of serrated portions extending toward the outer edge of the substrate. A second ground ring surrounds the first ground ring and possesses a second set of serrated portions extending toward the first serrated extending portions of the first ground ring, such that both the extending portions of the first and second serrated ground rings interlace coincidentally with each other and the wire bonding distances from the bonding pads of chip to the extending portions of the first and second serrated rings are comparable. A first power ring surrounds the second ground ring and possesses a third set of serrated portions extending toward the outer edge of the substrate. A second power ring surrounds the outer region of first power ring and possesses a fourth set of serrated portions extending toward the third serrated ring, such that both the extending portions of the third and fourth serrated rings interlace coincidentally with each other and the wire bonding distances from the bonding pads of chip to the extending portions of the third and fourth serrated rings are comparable. According to the second embodiment of the present invention, only three looping profiles are employed for the bonding wires connecting the bonding pads to the two ground rings, the two power rings and the fingers.
According to another aspect of the present invention, a plurality of power vias are dispersedly distributed in the power ring to electrically connect the power ring to the power plate, wherein at least two power vias are coupled together. The coupled power vias can reduce the damage to the wholeness of ground plate thus enables the best electrical performance of the ground plate. Moreover, the power vias are distributed radially with respect to the chip on the central of substrate so that the current can flow smoothly in the ground plate and the best electrical performance can thereby be achieved.
The present invention can significantly shorten the operation time for wire bonding, and reduce the height and the length of the bonding wire, thus the difficulty in wire bonding operation can be greatly decreased. This invention can also reduce the thickness of package body and thereby enhancing the packaging efficiency. Besides increasing the packaging efficiency, the present invention can prominently shorten the length of the bonding wire from bonding pads to the ground ring and the power ring, and thus decreases the corresponding inductance and noise to greatly enhance the electrical performance of semiconductor package. Since it can shorten the distance between the ground ring and the power ring, the corresponding inductance and capacitance therebetween can be respectively decreased and increased and a better frequency response can be achieved. The enhanced frequency response enables the semiconductor package to operate at a higher speed, with less power consumption and higher electrical performance.